Sample-Timing Skew in Time Interleaved ADC

In digital communication systems, Analog-to-Digital Converter (ADC) is the main interface between the analog domain and the digital domain. The continuous rising demand for high data rate communication systems has been creating the need for wide-band ADCs with a high sampling rate and high accuracy. These ADCs need to achieve high speed and high resolution along with having wide bandwidth and low distortion. While high-resolution ADCs can be built using specific techniques, the maximum conversion rate of an ADC is limited by the technology process.

The time-interleaved ADC architecture, initially proposed by Black and Hodges [1], is an effective way to implement an ADC that uses slower circuits and it can achieve sampling rates beyond the technological limits of a single ADC. As shown in Fig. 1, a time-interleaved ADC consists of M parallel ADCs, which are called “channels” and which have the same sampling rate. Yet they operate at interleaved sampling times, as though they were effectively a single ADC operating at M times higher sampling rate. The channels convert samples at the rate of fs/M samples per second, according to the sequential clock phases \phi_1, \phi_2, ... \phi_M, generated by a multiphase clock generator. Digital outputs from all channels are recombined by a digital multiplexer that provides a full data rate of fs samples per second.

Time Interleaved ADC

Figure 1. Time Interleaved ADC.

However, the time-interleaved structure has an important disadvantage. Mismatches among the channel ADCs, including offset and gain mismatches and sample-time error, generate undesirable noise and significantly degrade the effective resolution of the time-interleaved ADC [1-5]. These mismatches may change slowly over time due to temperature variation and aging, and careful layout or trimming methods are not sufficient to achieve low distortion.

Different techniques have been implemented to detect and correct gain and offset mismatches [6-11], but only few references [9, 12-14] have proposed practical solutions for correcting timing mismatches.

A single front-rank sample-and-hold can be used in front of the channel ADCs in order to eliminate the need for sample-time error correction [12-13]. However, the sample-and-hold needs to operate at the sampling rate of fs which needs much shorter settling time, compared with one which might be required by each channel ADC operating at the sampling rate of fs/M. Calibration is an alternative way to overcome the sample-time error problem in time-interleaved ADCs. Calibration of sample-time error requires both detection and correction of the error.

Sample-time error detection can be performed either in the foreground or the background. In foreground detection, a known sinusoidal signal is applied and the sample-time error is estimated from the tones caused by sample-time error in the output spectrum [15]. Alternatively, an accurate ramp signal can be used to measure sample-time error [16]. Knowing the slope of the ramp signal, we can estimate the sample-time error from differences of the channel ADC outputs. Generally, foreground calibration requires interruption in the normal process of the ADC, perhaps not an option in some communication systems.

The error detection can be performed in the background without interrupting the ADC conversion process. In background detection, the ramp signal is added to the ADC input [16]. This addition reduces the available dynamic range of the ADC. Few methods have been proposed to detect sample-time error using only the ADC output [9-10, 17-21], but these require either specific constraints on the input signal, oversampling of the input, or large hardware complexity. In the method proposed in [10], the input signal is assumed to be only a band-limited Wide-Sense Stationary (WSS) signal. This method is computationally complex and is sensitive to offset and gain mismatches. The method proposed in [9, 17] has been used only in a two-channel time-interleaved ADC. The ADC output is first chopped and then passed through a Hilbert transform filter. The filter output and the ADC output are multiplied in order to detect any sample-time error. The product has an average component which is proportional to the error. The scheme proposed in [18] can use only band-limited WSS signals which are not synchronous with the ADC clock signal. This scheme is based on the fact that the probability of zero crossing between two sampling instants for a stationary input signal has a bivariate normal distribution. This method equalizes the number of zero crossings among channel ADCs. Offset mismatch does not affect this method, while it remains sensitive to the gain mismatch. The schemes discussed in [19-20] require that the input signal be oversampled, and extensive matrix computation is needed to estimate sample-time error. The method in [20] is applicable only to narrow-band input signals. The method proposed in [11] is suitable for the ADCs used in digital communication systems. The mean square value of the error at the decision point (or slicer), which is due to both Inter Symbol Interference (ISI) and sample-time error, is used for error detection. A set of equalizers is employed to remove both the ISI and the sample-time error on each channel ADC. Complexity of these equalizers, working at the sampling rate of each channel ADC, is higher than the complexity required for removing only the ISI. The algorithm presented in [21] is different from previously mentioned methods and tries to match the frequency response of the channel ADCs. However, this algorithm assumes a WSS input signal and requires complex matrix computations.

Once the sample-time error has been detected, sample-time error correction can be performed mainly using two options. The sample-time error can be corrected by processing the digital output of the channel ADCs to interpolate the samples at correct sampling time [9-11, 16, 19-20]. Although this approach is portable and flexible, the interpolation process requires oversampling of the input signal. Alternatively, the sampling clock for each channel ADC could be adjusted using a fine-resolution Digitally-Controlled Delay Element (DCDE) or a phase shifter to correct sample-time error among different channels [12, 22]. This approach requires careful design of the clock generator block in order to limit the additive random jitter by the extra clock edge control circuitry.

References:
[1] W. C. Black, Jr., and D. A. Hodges, “Time interleaved converter arrays,” IEEE Journal of Solid-State Circuits, pp. 1022-1029, December 1980.
[2] A. Petraglia, and S. K. Mitra, “Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer,” IEEE Trans. on Instrumentation and Measurement, pp. 831-835, October 1991.
[3] N. Kurosawa, H. Kobayashi, K. Maruyama, K. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Trans. on Circuits and Systems-I, pp. 261-271, March 2001.
[4] B. Yu, and W. C. Black Jr., “Error analysis for time-interleaved analog channels,” Proc. IEEE Int. Symposium on Circuits and Systems, pp. 468-470, May 2001.
[5] C. Vogel, “The impact of combined channel mismatch effects in time-interleaved ADCs,” IEEE Trans. on Instrumentation and Measurement, pp. 415-427, February 2005.
[6] D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, “A digital background calibration technique for time-interleaved analog-to-digital converters,” IEEE Journal of Solid-State Circuits, pp. 1904-1911, December 1998.
[7] K. C. Dyer, D. Fu, S. H. Lewis, and P. J. Hurst, “An analog background calibration technique for time-interleaved analog-to-digital converters,” IEEE Journal of Solid-State Circuits, pp. 1912-1919, December 1998.
[8] J. Eklund, and F. Gustafsson, “Digital offset compensation of time-interleaved ADC using random chopper sampling,” Proc. IEEE Int. Symposium on Circuits and Systems, pp. 447-450, May 2000.
[9] S. M. Jamal, D. Fu, N. C. J. Chang, P. J. Hurst, and S. H. Lewis, “A 10-b 120-Msamples/s time-interleaved analog-to-digital converter with digital background calibration,” IEEE Journal of Solid-State Circuits, pp. 1618-1627, December 2002.
[10] J. Elbornsson, F. Gustafsson, and J. Eklund, “Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system,” IEEE Trans. on Circuits and Systems-I, pp. 151-158, January 2004.
[11] T. Tsai, P. J. Hurst, and S. H. Lewis, “Time-interleaved analog-to-digital converters for digital communications,” Proc. Conference on Circuits, Signals, and Systems, pp. 193-198, November 2004.
[12] K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Montijo, “A 20GS/s 8b ADC with a 1MB memory in 0.18m CMOS,” Proc. IEEE International Solid-State Circuits Conference, pp. 318-496, February 2003.
[13] K. Poulton, and J. J. Corcoron, “A 1-GHz 6-bit ADC system,” IEEE Journal of Solid-State Circuits, pp. 962-970, December 1987.
[14] S. Gupta, M. Choi, M. Interfield, and J. Wang, “A 1GS/s 11b time-interleaved ADC in 0.13m CMOS,” Proc. IEEE International Solid-State Circuits Conference, pp. 576-577, February 2006.
[15] Y. C. Jenq, “Digitl spectra of nonuniformly sampled signals: Fundamentals and high-speed waveform digitizer,” IEEE Trans. on Instrumentation and Measurement, pp. 245-251, June 1988.
[16] H. Jin, and E. K. F. Lee, “A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADC’s,” IEEE Trans. on Circuits and Systems-II, pp. 603-613, July 2000.
[17] S. M. Jamal, D. Fu, M. P. Singh, P. J. Hurst, and S. H. Lewis, “Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter,” IEEE Trans. on Circuits and Systems-I, pp. 130-139, January 2004.
[18] C. Wang, J. Wu, “A background timing-skew calibration technique for time-interleaved analog-to-digital converters,” IEEE Trans. on Circuits and Systems-II, pp. 299-303, April 2006.
[19] S. Huang, and B. C. Levy, “Blind calibration of timing offsets for four-channel time-interleaved A/D converters,” IEEE Trans. on Circuits and Systems-I, pp. 863-876, April 2007.
[20] V. Divi, and G. Wornell, “Scalable blind calibration of timing skew in high-resolution time-interleaved ADCs,” Proc. IEEE Int. Symposium on Circuits and Systems, pp. 3390-3393, May 2006.
[21] M. Seo, M. J. W. Rodwell, and U. Madhow, “Comprehensive digital correction of mismatch errors for a 400-Msamples/s 80-dB SFDR time-interleaved analog-to-digital converter,” IEEE Trans. on Microwave Theory and Techniques, pp. 1072-1082, March 2005.
[22] A. Haftbararadaran, and K. Martin, “A sample-time error compensation technique for time-interleaved ADC systems,” Proc. IEEE Custom Integrated Circuits Conference, pp. 341-344, September 2007.
[23] Simon Louwsma, Ed Tuijl, and Bram Nauta, Time-interleaved Analog-to-Digital Converters, Springer Netherlands; 2011 edition (September 8, 2010).

About the author

 Afshin Haftbaradaran is a staff engineer at Qualcomm. Before Qualcomm he has been working at AMD, and Snowbush Microelectronics. Afshin has a Ph.D. degree in Electrical Engineering from the University of Toronto.

If you have enjoyed reading this post, please subscribe to Minutify, so we can send you an email each time a new post is available.

4 thoughts on “Sample-Timing Skew in Time Interleaved ADC

  1. Pingback: Probiotic

  2. Pingback: Surviving The Final Bubble

  3. Pingback: kids playing black ops on ps4 call of duty

  4. Pingback: Indian Ocean

Comments are closed.